The Mobile Industry Processor Interface (MIPI) Alliance is a collaboration of mobile industry leaders having the objective of defining and promoting open standards for interfacing with mobile application processors. A mobile application processor is typically a system-on-a-chip (SoC) that executes applications in a mobile operating system environment. The MIPI Alliance establishes specifications for standard hardware and software interfaces in mobile processing environments to speed deployment of new services to mobile users. In such mobile processing environments, data is communicated between and among chips forming the SoC over high speed serial links. While this high speed serial data must be communicated, there is also a need for low speed and low power communication over these same data links, such as to transfer link management information, lower priority or speed-critical data, and possibly other types of low speed data as well.
Different ways or protocols for communicating this serial data have been proposed and utilized, such as protocols including a data clock or data strobe accompanying the data being communicated as well as self-clocking protocols (i.e., no separate data clock or strobe) like Pulse Width Modulation (PWM) and Pulse Width and Amplitude Modulated (PWAM). In many of these prior approaches, a phase-locked loop (PLL) or delay-locked loop (DLL) in both a transmitter transmitting the data and in a receiver receiving the data are required. In one such situation, a mobile physical layer (M-PHY) standard communicates pulse width modulated data signals, with the duty cycle of each pulse width modulated signal determining whether a binary 1 or a binary 0 is being communicated. In the present description the acronym PWM is utilized to refer to both the terms “pulse width modulation” and “pulse width modulated.”
One prior approach of sensing or demodulating these PWM data signals being communicated according to the M-PHY standard is to utilize a counter to generate a count value when the PWM data signal is high and a count value when the PWM data signal is low, and to compare the two counts to determine whether the PWM signal is communicating a binary 1 or a binary 0. An up/down counter could also be utilized. With this approach, however, the frequency of a clock signal that clocks the counter, or the number of phases of the clock signal, may need to be eight or more times higher than the frequency of the PWM data signal. For example, if the duty cycle of the PWM data signal may go as low as ¼ (0.25) the period or unit interval (UI) of the data signal then the clock signal would need to be twice the frequency of this signal (2×(1/(¼UI)) or eight times the frequency (1/UI) of the PWM data signal. Circuitry to generate this clock signal may consume relatively large amounts of power. Moreover, the clock signal must be synchronized with the PWM data signal so the PWM data signal must include a synchronizing preamble. Some applications, however, require that no such preamble be utilized due to bandwidth constraints. Another approach utilizes a phase locked loop (PLL) to lock onto the PWM data signal and to then appropriately sample the PWM data signal. These PLLs may consume relatively large amounts of power and also require relatively complex circuitry. Another technique is to use an analog integrator to extract the middle of a data clock period for use in data extraction, but such an approach also may consume a relatively large amount of power. Accordingly, there is a need for improved techniques of reliably capturing serial PWM data signals.